The present invention relates to integrated circuits, in particular in electronic control units, being preferably components of motor vehicle control units. In particular, the control units concern control units for motor vehicle brake systems. Control units of this type are, among others, appropriate for performing safety-critical control operations. The motor vehicle control units preferably comprise control programs such as ABS, TCS, ESP, and similar systems. Due to the high safety requirements, the control systems formed of the integrated circuits comprise safety circuits, which help detecting failure or a defect and initiate appropriate measures such as deactivation of the overall system or an emergency operation due to measures that partly preserve the operation of the controlled system.
Control systems with integrated circuits comprising microprocessors are generally known for the above-mentioned tasks. To prevent malfunctions or to detect them, it is suitable to arrange for at least two processor cores. Admittedly, three or more processor cores would increase safety even further, however, this is not always desired for cost reasons in connection with the large scale manufacture being customary in the field of motor vehicle technology. Therefore, there is a demand for low-cost circuits with a high safety level.
For example, a concept of a control system, which is composed of two integrated circuits accommodated in separate chip housings, has stood the test. This concept achieves the advantage of a spatial separation of power elements (Power FETs etc.) and highly integrated microprocessor components μC, memories, etc.).
The error-relevant communication favorably takes place by way of two error lines ERR and ERR_N in the above example.
The invention is based on a system as mentioned above and improves it in order to further improve the immunity to interference.
According to the invention, this object is achieved by a method of improving the immunity to interference of an integrated circuit (16), wherein error signals are transferred between at least one microprocessor chip or multiple processor μC (1) and at least one further component (2) in the form of one or more error signals. In the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. The invention is also achieved by an integrated circuit including at least one microprocessor chip or multiple processor microcontroller (1) or microprocessor module and at least one additional separate component (2) or a mixed-signal module integrated in the same component and comprising in particular separately arranged power elements, and one or more pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6′) one after the other through at least one error line (3, 4).
Further, the control system can possess one or more monitoring circuits, which are incorporated in particular on one or more additional separate chips (watchdog).
In the prior art electronic controller, processor chip and power chip are advantageously interconnected by way of the lines ERR and ERR_N. In this arrangement, the power chip must be able to detect pulses of the processor chip, which are transmitted on ERR or ERR_N, respectively, with a minimum pulse width of e.g. Tmin=30 nanoseconds. It is possible that external electrostatic, magnetic, or electromagnetic interferences (e.g. frictional electricity, ESD) intervene into the system and have undesirable effects.
According to the invention, methods as well as integrated circuits are described in order to enhance the immunity to interference, especially the immunity to interference of the signals ERR and ERR_N. This brings about better system availability.